Surface treatment of low-k siof to prevent metal interaction

ABSTRACT

A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to the field ofsemiconductor chip processing, and more particularly, to the processingfor an interlayer dielectric.

[0003] 2. Description of the Related Art

[0004] Fluorinated SiO₂ (typically PECVD or HDP) can be used to lowerthe dielectric constant of SiO₂ from, for example, 4.0 to 3.6-3.8. Thelowering of the dielectric constant is advantageous for a number ofreasons, including to reduce the capacitance of the semiconductor deviceand thereby increase its performance.

[0005] However, fluorine in SiO₂ will react with PVD barrier metals (Ti,TiN, Ta, TaN, Al, Cu, etc.) which are subsequently deposited on thesurface of the fluorinated SiO₂. This reaction between fluorine and thebarrier metals will cause delamination on flat SiOF surfaces, as well asinside via holes.

SUMMARY OF THE INVENTION

[0006] Briefly, the present invention comprises, in one aspect, a methodfor using low dielectric SiOF in a process to manufacture semiconductorproducts, comprising the steps of obtaining a layer of SiOF; anddepleting the fluorine from a surface of the SiOF layer.

[0007] In a further aspect of this inventive method, the depleting stepcomprises the step of treating the surface of the layer of SiOF with aplasma containing hydrogen to yield a treated surface.

[0008] In a yet further aspect of the present invention, the methodcomprises the step of passivating the treated surface.

[0009] In a further aspect of the present invention, the passivatingstep comprises the step of applying substantially pure nitrogen plasmato the treated surface.

[0010] In a yet further aspect of the present invention, the nitrogenplasma is applied at a lower plasma bias power and a higher pressurethan the hydrogen-containing plasma used in the treating step.

[0011] In a further aspect of the present invention, the treating stepis carried out in a CVD deposition chamber.

[0012] In a yet further aspect of the present invention, the depletingstep forms a depletion layer that is greater than or equal to 30Angstroms in thickness.

[0013] In a further aspect of the present invention, the passivatingstep comprises the step of forming a passivation layer that is less thanor equal to 25 Angstroms in thickness.

[0014] In a further embodiment of the present invention, a method isprovided for using low dielectric SiOF in a process to manufacturesemiconductor integrated circuit chips, comprising the steps of:obtaining a layer of SiOF; treating in a CVD-TiN deposition chamber asurface of the layer of SiOF with a plasma containing hydrogen todeplete fluorine from the surface; passivating the treated surface withsubstantially pure N₂ plasma; and depositing a layer of TiN.

[0015] In a yet further embodiment of the present invention, asemiconductor chip is provided comprising: an integrated circuit with atleast a first and second layers, and with a dielectric layer of SiOFdisposed between said two layers, wherein the SiOF dielectric layerincludes a first region at one edge thereof which is depleted offluorine to a predetermined depth.

[0016] In a further aspect of this inventive embodiment, thepredetermined depth of the first region is greater than or equal to 30Angstroms.

[0017] In yet a further aspect of the present invention, the depth ofthe second region is less than or equal to 25 Angstroms.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a process flow diagram for a method in accordance withthe present invention.

[0019]FIG. 2 is a cross-section of a select group of layers on asemiconductor chip.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0020] The present invention will be described in its context of usewith an interlayer dielectric layer in a conducting layer stack on asemiconductor chip. However, the invention has broad application in anysituation where SiOF is utilized as a layer.

[0021] Referring now to the drawings, FIG. 1 is a process flow diagramfor a method in accordance with the present invention. FIG. 2illustrates a semiconductor chip 10 in accordance with present inventioncomprising a bulk substrate and various process layers, designatedgenerally by the numeral 12. A further layer 14 of same type is thendeposited. By of example, this further layer 14 might be a conductinglayer such as a metallic layer. For purposes of describing the presentinvention, an SiOF layer 16 is shown as being deposited on this layer14. The SiOF layer 16 may be formed, by way of example, but not by wayof limitation, by introducing a fluorine species during an SiO₂ PECVD orHDP. Typically, after this SiOF deposition step, vias are etched throughthe SiOF layer 16. This via etch step is followed by a resist strip stepand a solvent clean step, in the well known manner.

[0022] The present invention then requires application of a process todeplete the fluorine form the top surface of the SiOF layer 16 to yielda depleted layer 18 having a desired thickness. In a preferredembodiment this thickness of the depleted layer 18 is equal to orgreater than 30 Angstroms.

[0023] In a preferred embodiment, the step used to form the depletionlayer 16 is accomplished by treating the surface of the SiOF layer 16with a plasma containing hydrogen. For example, the plasma may be purehydrogen, or it may be a diluted H₂ plasma, for example an H₂/N₂ plasma.The purpose of diluting the hydrogen plasma is to make the hydrogen lessvolatile.

[0024] The hydrogen in the plasma will bond with the fluorine atoms toform HF, which, because of its high vapor pressure and low boilingpoint, will be vaporized and evacuated from the system.

[0025] In a preferred embodiment, the hydrogen plasma treatment isperformed in a CVD deposition chamber, such as, for example, an AppliedMaterial CVD deposition chamber. The CVD chamber may be the same chamberused to be used to deposit a subsequent conducting layer, such as TiN.Preferably the CVD chamber for the plasma treatment should have aslightly elevated temperature (5-50° C. higher) relative to thetemperature used to deposit the subsequent conducting layer. Forexample, if a temperature falling in the range of 375° C. to 450° C. isto be used to deposit a subsequent conducting layer 22, then a slightlyelevated temperature that is 5° C. to 50° C. higher than the conductinglayer CVD deposition temperature is used during the hydrogen plasmatreatment step. The purpose of the use of this elevated temperature isto lower the potential that heating during the subsequent conductinglayer deposition step will drive the fluorine atoms from the bulk SiOFlayer 16 into the fluorine-depleted layer 18.

[0026] The other parameters for the hydrogen plasma treatment step willbe determined empirically. Typically, the pressure in the CVD chamberwill be in the millitorr to torr range, the energy parameter will be inthe several hundred watt range, and plasma treatment time will rangefrom 20 seconds to several minutes. Optimized parameters will bedetermined based on the desired thickness of the depletion layer 18.

[0027] In a preferred embodiment, the depleted layer 18 is thenpassivated to form a passivation layer 20 which is less than thethickness of layer 18. One purpose of the passivation is to bondnon-volatile atoms into the depleted layer 18 to lessen the potentialfor fluorine atoms from the bulk SiOF layer 16 diffusing up into thedepleted layer 18 and thereafter reacting with the conducting layeratoms of the subsequently deposited layer 22. This passivation step maybe carried out by switching to a pure N₂ plasma in the CVD chamber toform SiON to a thickness that is less than the thickness of thedepletion layer 18. For example, the passivation layer 20 could have athickness of 25 Angstroms or less, for example. Typically, a highersource power will be used in the CVD chamber, for example, 300-400watts, to cause the nitrogen to bond with the SiO surface to yield anSiON dielectric barrier. This passivated dielectric barrier layerlessens the potential that fluorine atoms will diffuse up to the surfaceof layer 16 and react with, for example, a Ti or TiN barrier metal.

[0028] Note that less bias power (the bias power is different than theplasma power) and a higher pressure condition should be used to treatsidewalls and vias in the SiOF layer 16. For example, a bias power ofless than 100 watts could be utilized. One purpose for the lower biaspower is to make the plasma less directional so that it will affect thesidewalls.

[0029] The exact thickness of the passivation layer 20 may be optimizedempirically. Note that a SIMS analysis may be performed to measure thethickness of the depletion layer 18 and the thickness of the passivationlayer 20. Ultimately, optimization is achieved when the depletion andpassivation layer thickness are such that it can be assumed that thesubsequent layer 22 will not peel off during the remaining process stepsfor the semiconductor chip.

[0030] A typical device realized using the present invention methodmight have bulk SiOF layer 16 of 8,000 Angstroms to 15,000 Angstroms,with a depletion layer 18 of 50 Angstroms, and a passivation layer 20 of25 Angstroms.

[0031] Next, a conducting layer 22 is deposited. By way of example, anin-situ deposition of optimized CVD-TiN may accomplished in thepreviously mentioned CVD chanber using a nitrogen-rich initial layer.This deposition would then be followed by a standard blanket tungstendeposition to form a layer 24. Note that the present invention is notlimited to TiN and Ta. A variety of metals are available to form theseconducting layers, including Ti, TiN, Ta, Al, and Cu, for example.

[0032] It should be noted that although the present invention isparticularly advantageous when used to form an SiOF inter-metaldielectric layer, it has application in any situation where the fluorineatoms in an SiOF layer are causing interaction and/or adhesion problemswith other layers.

[0033] The foregoing description of a preferred embodiment of theinvention has been presented for purposes of illustration anddescription. It is not intended to be exhaustive or to limit theinvention to the precise form disclosed, and modifications andvariations are possible in light of the above teachings or may beacquired from practice of the invention. The embodiment was chosen anddescribed in order to explain the principles of the invention and itspractical application to enable one skilled in the art to utilize theinvention in various embodiments and with various modifications as aresuited to the particular use contemplated. It is intended that the scopeof the invention be defined by the claims appended hereto, and theirequivalents.

We claim:
 1. A method for using low dielectric SiOF in a process tomanufacture semiconductor products, comprising the steps of: obtaining alayer of SiOF; and depleting the fluorine from a surface of the SiOFlayer.
 2. A method as defined in claim 1 , wherein said depleting stepcomprises the step of treating the surface of said layer of SiOF with aplasma containing hydrogen to yield a treated surface.
 3. A method asdefined in claim 1 , further comprising the step of passivating thetreated surface.
 4. A method as defined in claim 3 , wherein saidpassivating step comprises the step of applying substantially purenitrogen plasma to the treated surface.
 5. A method as defined in claim4 , wherein said nitrogen plasma is applied at a lower plasma bias powerand a higher pressure than said hydrogen-containing plasma used in saidtreating step.
 6. A method as defined in claim 2 , wherein said treatingstep is carried out in a CVD-TiN deposition chamber.
 7. A method asdefined in claim 6 , wherein said treating step is carried out at ahigher temperature than a temperature for CVD-TiN.
 8. A method asdefined in claim 1 , further comprising the step of depositing a TiNlayer on said treated surface.
 9. A method as defined in claim 8 ,further comprising the step of depositing a tungsten layer over said TiNlayer.
 10. A method as defined in claim 6 , further comprising the stepof depositing a TiN layer on said treated surface.
 11. A method asdefined in claim 1 , wherein said depleting step forms a depletion layerthat is greater than or equal to 30 Angstroms in thickness.
 12. A methodas defined in claim 3 , wherein said passivating step comprises the stepof forming a passivation layer that is less than or equal to 25Angstroms in thickness.
 13. A method as defined in claim 3 , whereinsaid depleting step forms a depletion layer that is greater than orequal to 30 Angstroms in thickness, and wherein said passivating stepcomprises the step of forming a passivation layer that is less than orequal to 25 Angstroms in thickness.
 14. A method for using lowdielectric SiOF in a process to manufacture semiconductor integratedcircuit chips, comprising the steps of: obtaining a layer of SiOF;treating in a CVD-TiN deposition chamber a surface of said layer of SiOFwith a plasma containing hydrogen to deplete fluorine from said surface;passivating said treated surface with substantially pure N₂ plasma; anddepositing a layer of TiN.
 15. A method as defined in claim 14 , whereinsaid treating step is carried out at a higher temperature than atemperature for CVD-TiN.
 16. A semiconductor chip comprising: anintegrated circuit with at least a first and second layers, and with adielectric layer of SiOF disposed between said two layers, wherein saidSiOF dielectric layer includes a first region at one edge thereof whichis depleted of fluorine to a predetermined depth.
 17. A semiconductorchip as defined in claim 16 , wherein said first and second layers aremetallic layers.
 18. A semiconductor chip as defined in claim 16 ,wherein said first region includes a second region, extending from saidedge to a depth which is less than said depth of said first region, saidsecond region being passivated.
 19. A semiconductor chip as defined inclaim 16 , wherein said second region is passivated with nitrogen.
 20. Asemiconductor chip as defined in claim 17 , wherein said second layer isadjacent to said fluorine depleted region and is comprised of TiN.
 21. Asemiconductor chip as defined in claim 16 , wherein said predetermineddepth of said first region is greater than or equal to 30 Angstroms. 22.A semiconductor chip as defined in claim 18 , wherein said predetermineddepth of said first region is greater than or equal to 30 Angstroms andsaid depth of said second region is less than or equal to 25 Angstroms.23. A semiconductor chip as defined in claim 18 , wherein said depth ofsaid second region is less than or equal to 25 Angstroms.